台积电介绍3nm后的互连方案

来源：内容由半导体行业观察（ID：icbank） 编译自semiwiki ，谢谢。

高级节点的互连和通孔光刻的进一步缩放受到提供支持图案后关键尺寸变化和掩模重叠公差的工艺窗口的要求的挑战。在最近于旧金山举行的国际电子器件会议 (IEDM) 上， 台积电 展示了其工艺开发活动的研究更新，以实现即将到来的节点的“自对准通孔”(self-aligned via：SAV)，互连+通孔流程可提高可制造性.本文总结了他们演讲的亮点。

介绍

过孔的可制造性需要解决多种光刻、电气和可靠性措施：

• 对叠加变化的容忍度（又名“边缘放置错误”，或 EPE）
• 通孔电阻的一致性
• 通孔到相邻金属介电特性的稳健性
• 漏电流
• 击穿前的最大外加电压 (Vbd)

介电可靠性，测量为随时间变化的介电击穿 (TDDB：time-dependent dielectric breakdown）

而且当然，

• 异常收益

（请注意，这些问题对于较低层金属和通孔的缩放最为严重，在本文的图中用“Mx”表示。）

通孔和相邻金属线之间的重叠定位会影响介电击穿——包括Vbd 和 TDDB。下图说明了具有代表性的 EPE 的传统通孔的覆盖与介电击穿问题。

“自对准”通孔（与相邻金属线具有独特的电介质）将提供更大的工艺范围来解决上面列出的挑战。

台积电 SAV 制程

TSMC SAV 工艺流程有两个关键步骤——在金属线上沉积“阻挡层”和选择性沉积电介质上电介质。

• 自组装单层（SAM）沉积在金属上

独特的工艺化学步骤在暴露的金属表面上沉积单层阻隔材料。该过程基于悬浮在溶液中的有机化学链对金属的亲和力。分子链吸附在金属表面，并自组装成一个有组织的域。随着时间的推移，分子会吸附，它们会成核成组并生长，直到金属表面被单层覆盖。（由于范德华力，中性有机固体之间的弱净吸引力，单层紧密堆积。）

该 SAM 单层将用作阻挡材料。它的成分需要承受下一步的热暴露 - 在氧化物上的选择性介电沉积。

• 选择性介电对介电 (DoD) 沉积

先进的节点已经利用了几代的原子层沉积 (ALD) 步骤。将气相“前体”引入处理室。由于化学吸附，独特的前体单层沉积在晶片表面。前体粘附在表面上，但不粘附在自身上——没有连续的前体层沉积。然后清除腔室中多余的前体，随后引入共试剂。化学反应导致所需反应产物的最终单层保留在表面上，而多余的共试剂和反应副产物则被泵出。可以重复该循环以沉积多个“原子”层。ALD 已被广泛用于金属和薄氧化物介电材料的沉积。

一个活跃的研究领域是提供选择性的原子层沉积，其中前体只附着在特定的材料表面。目标是抑制特定区域的前体吸附 - 在这种情况下，是金属上的 SAM 分子。

台积电探索了一种选择性沉积化学工艺，用于电介质上电介质层的构建。下图中的图像描绘了在现有表面氧化物上方提升介电层的工艺流程。

SAM 阻挡层阻止了在暴露的电介质上的选择性沉积。如前所述，阻挡层必须经受住电介质上电介质选择性沉积的高温。TSMC 表示，更高的 DoD 工艺温度提高了电介质基座对周围用于通孔的低 K 层间电介质的蚀刻选择性，接下来将讨论。

上图中标记为“DoD”的图像说明了在电介质上电介质沉积之后以及在添加低 K 电介质之前去除硅片上的 SAM 阻挡材料之后的硅片。

右图显示了在低 K 电介质沉积/蚀刻和通孔图案化之后的最终通孔连接。由于与低 K 材料相比蚀刻速率较低，因此添加了 DoD 材料服务器作为合适的“蚀刻停止”。该图像说明了存在显着覆盖偏移的通孔到相邻金属电介质。

下图说明了增加的电介质上电介质层如何提高通孔鲁棒性。“对照”透射电子显微镜图像（没有 DoD）显示原始电介质的过孔蚀刻过多，与相邻的 Mx 线几乎没有隔离 - 不是特别容忍重叠错误。DoD TEM 图像显示隔离度大大提高。

SAV 过程的实验电气和可靠性数据

下面的各种图显示了来自台积电 SAV 工艺开发团队的实验数据。控制数据反映了没有选择性 DoD 层沉积的通孔图案化工艺的标准。

• 通过电阻

单通孔和通孔链（良率评估）电阻值均显示控制和 DoD 工艺之间没有差异。

• 过孔到相邻的 Mx 可靠性（漏电流、Vbd、TDDB）

为了评估工艺窗口，TSMC 团队通过有意的过孔到 Mx 覆盖偏移评估了漏电流和 Vbd。请注意，控制过程不支持 4nm 重叠公差。

为确保额外的 DoD 工艺步骤不会对现有 Mx 金属的特性产生不利影响，台积电共享了有和没有 DoD 工艺的金属线的评估数据。下图显示对金属线电阻或 TDDB/电迁移可靠性没有影响。

总结

3nm 节点以下的持续互连缩放将需要独特的工艺开发研究，以在存在（高达 4nm）重叠错误的情况下保持电气和可靠性规范。对低 K 层间电介质的需求是给定的——然而，这些材料中的通孔蚀刻并不是特别耐受 EPE。

台积电已经展示了一种潜在的“自对准通孔”工艺流程，其中包含额外的 DoD 材料。DoD 的蚀刻速率差异导致了更强大的通孔到相邻金属的可靠性。该工艺流程采用两个独特的步骤——金属表面阻挡材料的 SAM 和电介质上电介质的选择性 ALD。

希望选择性 ALD 流程将很快从研发过渡到生产制造——这种化学物质对先进节点缩放的潜在影响是巨大的。

附：英文原文

The further scaling of interconnect and via lithography for advanced nodes is challenged by the requirement to provide a process window that supports post-patterning critical dimension variations and mask overlay tolerances.  At the recent international Electron Devices Meeting (IEDM) in San Francisco, TSMC presented a research update on their process development activities to realize a “self-aligned via” (SAV) for upcoming nodes, with an interconnect + via flow that provides improved manufacturability.[1]  This article summarizes the highlights of their presentation.

Introduction

The manufacturability of vias needs to address multiple litho, electrical, and reliability measures:

• tolerance to overlay variation (aka, “edge placement error”, or EPE)

• consistency of via resistance

• robustness of via-to-adjacent metal dielectric properties

• leakage current

• maximum applied voltage before breakdown (Vbd)

• dielectric reliability, measured as time-dependent dielectric breakdown (TDDB)

and, of course,

• exceptional yield

(Note that these issues are most severe for the scaling of lower level metals and vias, denoted as “Mx” in the figures in this article.)

The overlay positioning between a via and an adjacent metal line impacts the dielectric breakdown – both Vbd and TDDB.  The figure below illustrates the overlay versus dielectric breakdown issue of a conventional via, for a representative EPE.

A “self-aligned” via (with a unique dielectric to an adjacent metal line) would provide greater process latitude to address the challenges listed above.

TSMC SAV Process

There are two key steps to the TSMC SAV process flow – the deposition of a “blocking layer” on metal lines and the selective deposition of dielectric-on-dielectric.

• self-assembled monolayer (SAM) deposition on metal

A unique process chemistry step deposits a monolayer of a blocking material on an exposed metal surface.  This process is based on the affinity of organic chemical chains suspended in a solution to the metal.  The molecular chains are adsorbed on the metal surface, and self-assemble into an organized domain.  As the molecules adsorb over time, they will nucleate into groups and grow until the metal surface is covered with a monolayer.  (The monolayer packs tightly due to the van der Waals forces, the weak net attractive electric force between neutral organic solids.)

This SAM monolayer will serve as a blocking material.  Its composition needs to withstand the thermal exposure of the next step – the selective dielectric deposition on oxide.

• selective dielectric-on-dielectric (DoD) deposition

Advanced nodes have leveraged atomic layer deposition (ALD) steps for several generations.  A gas phase “pre-cursor” is introduced into the process chamber.  Due to chemisorption, a unique pre-cursor monolayer is deposition on the wafer surface.  The pre-cursor adheres to the surface, but not to itself – no successive pre-cursor layers are deposited.  The chamber is then purged of the excess pre-cursor, and a co-reagent is subsequently introduced.  The chemical reaction results in a final monolayer of the desired reaction product that remains on the surface, while the excess co-reagent and reaction by-products are pumped out.  The cycle can be repeated to deposit multiple “atomic” layers.  ALD has been widely adopted for the deposition of metal and thin-oxide dielectric materials. A key advantage of current ALD processes is they operate uniformly and conformally on the exposed wafer surface.

An active area of research is to provide selective area atomic layer deposition, where the pre-cursor only adheres to a specific material surface.  The goal is the pre-cursor adsorption is suppressed on specific areas – in this case, the SAM molecules on the metal.

TSMC explored a selective deposition chemical process, for dielectric-on-dielectric layer buildup.  The images in the figure below depict the process flow to raise a dielectric layer above the existing surface oxide.

The SAM blocking layer precludes the selective deposition on the exposed dielectric.  As mentioned earlier, the blocking layer must withstand exposure to the elevated temperature of the dielectric-on-dielectric selective deposition.  TSMC indicated that higher DoD process temperatures improve the etch selectivity of the dielectric pedestal to the surrounding low-K inter-level dielectric for the via, to be discussed next.

The image labeled “DoD” in the figure above illustrates the wafer after dielectric-on-dielectric deposition and after removal of the SAM blocking material over the wafer, prior to the addition of the low-K dielectric.

The image on the right shows the final via connection, after low-K dielectric dep/etch and via patterning.  The added DoD material server as a suitable “etch stop”, due to the lower etch rate compared to the low-K material.  This image illustrates the via-to-adjacent metal dielectric, in the presence of a significant overlay shift.

The figure below illustrates how the added dielectric-on-dielectric layer improves via robustness.  The “control” transmission electron microscopy image (without the DoD) shows excessive via etch of the original dielectric, with little isolation to the adjacent Mx line – not particularly tolerant of overlay error.  The DoD TEM image shows vastly improved isolation.

Experimental Electrical and Reliability Data for the SAV Process

The various figures below show the experimental data from the TSMC SAV process development team.  The Control data reflects the standard via patterning process without the selective DoD layer deposition.

• via resistance

Both single via and via chain (yield assessment) resistance values show no difference between the control and DoD processes.

• via-to-adjacent Mx reliability (leakage current, Vbd, TDDB)

To assess the process window, the TSMC team evaluated the leakage current and Vbd with an intentional via-to-Mx overlay shift.  Note that the control process would not support a 4nm overlay tolerance.

To ensure the additional DoD process steps did not adversely impact the characteristics of the existing Mx metal, TSMC shared evaluation data of metal lines with and without the DoD process.  The graphs below show there was no impact to metal line resistance or TDDB/electromigration reliability.

Summary

Continued interconnect scaling below the 3nm node will necessitate unique process development research to maintain electrical and reliability specs in the presence of (up to 4nm) overlay error.  The need for low-K interlevel dielectrics is a given – yet, the via etch in these materials is not especially tolerant of EPE.

TSMC has demonstrated a potential process flow for a “self-aligned via” with an additional DoD material.  The etch rate differential of the DoD results in more robust via-to-adjacent metal reliability.  This process flow utilizes two unique steps – the SAM of a blocking material on metal surfaces, and the selective ALD of a dielectric-on-dielectric.

Hopefully, selective ALD flows will transition soon from R&D to production fabrication – the potential impact of this chemistry for advanced node scaling is great.

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